system verilog - Interaction between 2 UVM registers -

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i trying implement uvm ral project, , faced problem. example have 2 registers - reg , reg b. create classes both, device spec value in field a.field1 mapping b.field2. how can implement in uvm ral. thanks.

you looking use aliased registers. concept described in uvm user guide in section 5.7.3 .(page 114 ) http://accellera.org/images/downloads/standards/uvm/uvm_users_guide_1.1.pdf

the example in umm user guide uses couple of concepts , same concept can used generate aliasing a.field1 , b.field2.

  • a call mechanism
    call can set post predict function of reg b.field2 . every time ,after value of b.field2 changes post-predict function triggered. in post predict function field value of register ( a.field1) updated [ calling field1.predict ]reflecting change/linkage. ( assuming a.field1 dependent/alias of b.field2)
  • wrapper class
    create wrapper class connect fields both these registers (a & b - a.field1 b.field2) , instantiate wrapper class. wrapper class registers callback register b field2. if register model auto generated wrapper class can instanced outside register model , else in example inside model itself.

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